Thermal Characterization of a Three-Dimensional (3D) Chip Stack

In order to determine appropriate cooling solutions for 3D chip stacks in various cases, it is important to have a better understanding of the total thermal resistance of a 3D chip stack. For this purpose, precise thermal resistance measurements and modeling of each component of a 3D chip stack are important. The thermal resistance of interconnection is considered to be one of the thermal resistance bottlenecks of a 3D chip stack. In this study, a steady-state thermal resistance measurement method is employed for the thermal resistance measurement of interconnection. The thermal resistance of the 200 μ m pitch C4’s (Pb97Sn3) jointed samples are measured and the thermal conductivity of C4’s is derived to be 18 – 24 W/mK. With regard to the thermal resistance of a silicon substrate, the thermal resistance of a silicon substrate with various interconnection pitches and diameters has already been modeled by considering the concentrated heat flow to interconnection, as presented in ICEP 2008.[15] Based on the modeled data, the thermal resistance reduction by underfill with various interconnection pitches and diameters is also studied.